What is an Advanced RISC Machine?

Oct 11, 2019 12:10:09 AM / by KernelCare Team


Electrical engineering is a field packed with acronyms. “Advanced RISC Machine” is an older name for the modern-day ARM processor, which represents the leading form of RISC architecture. “RISC” stands for reduced instruction set computer, and refers to a type of microprocessor architecture that optimizes performance by limiting the number of cycles per instruction within its CPU programs. 

The profusion of interlinked names has an interesting history. Today, ARM Holdings – owned by the behemoth SoftBank Group, via their Vision Fund – are the global leader in microprocessor and graphics processing unit (GPU) design. But ARM started out life in the late seventies as a now-defunct British company called Acorn, who developed a pioneering RISC computer. (The Acorn RISC was used in the Acorn Archimedes, a 32-bit early home computer whose name might trigger nostalgia in older readers.) In the nineties, after incorporation, the company replaced “Acorn” with “Advanced” and the processor became known as an Advanced RISC Machine. In 1998, after the company’s IPO, their name became simply "ARM Holdings”, or “ARM” for short. The name of the architecture/processor followed suit, changing its name once again to simply “ARM.”

The Benefits of RISC

A CPU runs a set of programs, each of whose complexity depends on the set of instructions comprising that program, and also the number of cycles per instruction. To improve CPU performance, you can either reduce the number of instructions per program, or the number of cycles per instruction. 

A complex instruction set computing (CISC) architecture takes the former route, and tries to reduce the number of instructions per program. This architecture bundles instructions together, which is more work for the hardware, but less work for the RAM.

Compared to a CISC architecture, processors with a RISC architecture optimize performance not by limiting the amount of instructions per program, but the amount of cycles per instruction. A single instruction only takes a single CPU cycle. Operations are only performed on registers, never directly on the memory.

With RISC, compilers have to spend more time breaking down complex instructions into single units. This can be a lot of work. 

However, the decoding is minimal. And here’s the crux: In a chip, transistors are required to decode instructions. So with a RISC architecture, you use far fewer transistors than with a CISC architecture. 

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RISC = Perfect for embedded systems

Fewer transistors means a smaller build. It also means reduced cost, lower power consumption, and lower heat dissipation. This makes the RISC architecture perfect for chips built into embedded systems, which need to be light, portable and battery-powered (think phones and laptops).

These days, to all intents and purposes, “advanced RISC machine” is essentially synonymous with an ARM processor. The ARM instruction set architecture is by some distance the world’s leading form of RISC architecture, with more than 100-billion ARM processors in circulation. ARM processors are licensed by ARM (the company) to other companies, who then utilise it within systems-on-chips (SoC) and systems-on-modules (SoM). (They also design cores that implement the ARM instruction set.) 

The ARM architecture is by far the most popular choice for embedded mobile devices such as Android, Chrome OS, Firefox OS, and Windows Mobile. Since 2012, the architecture has been also supported by several Linux distributions, such as Debian, Gentoo, Ubuntu and Raspbian.

KernelCare Team

Written by KernelCare Team